The present invention relates generally to the field of field-effect transistors (FETs, NFETs, PFETs), and more particularly to trench structures, for FETs, with relatively large lattice mismatch in their constituent materials.
III-V semiconductors have larger lattice constants than silicon, so integrating them on silicon is challenging. Methods for integrating III-V semiconductors on silicon have included blanket III-V growth and aspect ratio trapping (ART). Many semiconductor materials, such as silicon (Si) have, at the atomic level, a lattice structure. When two different semiconductor materials are intermingled, or placed in close proximity, it is generally better if the lattice constants of the two semiconductor materials are compatible, as such compatibility is understood by those of skill in the art. Aspect ratio trapping is an effective technique to trap threading dislocations, thereby reducing the dislocation density of lattice mismatched materials grown on silicon. The ART technique can be performed using thinner III-V layers. Trenches are employed for trapping misfit threading dislocations by stopping their propagation. The III-V material is grown in narrow trenches. The dislocations end at the trench walls, but fairly high defect densities up to 100,000,000/cm2 can still be observed. The present invention shows a structure to further reduce those defect densities. The performance of devices fabricated using dissimilar semiconductor materials can be materially affected by defects that cause abrupt changes in electrical and/or optical properties. Adverse effects due to misfit defects and threading dislocations should be minimized or avoided in the fabrication of electronic devices incorporating such semiconductor materials.
NFETs made using silicon and III-V compounds are known, best known is InGaAs. III-V materials are chemical compounds with at least one group III (IUPAC (International Union of Pure and Applied Chemistry) group 13) element and at least one group V element (IUPAC group 15). NFETs are considered a high performance option for future technology nodes (7 nm (nanometers) and beyond). Co-integration of III-V with silicon deals with a known challenge due to the high lattice mismatch of some III-V semiconductor materials and silicon (and germanium (Ge) and silicon-germanium (SiGe)). Aspect ratio trapping (ART) is a known technique that can be used to counter and/or overcome lattice mismatch issues. In currently conventional ART structures, trenches with parallel sidewalls are formed.
NFETs conventionally include trench structures that use III-V semiconductor material, with high electron mobility, such as GaAs (gallium arsenide), InGaAs (indium gallium arsenide) or InAs (indium arsenide). Some conventional PFETs also include trench structures that use III-V semiconductor material, like InGaSb (indium gallium antimonide), which has a high hole mobility.